We like the ICE40 FPGA from Lattice for two reasons: there are cheap development boards like the Icestick available for it and there are open source tools. We’ve based several tutorials on the Icestorm toolchain and it works quite well. However, the open source tools don’t always expose everything that you see from commercial tools. You sometimes have to dig a little to find the right tool or option.

Sometimes that’s a good thing. I don’t need to learn yet another fancy IDE and we have plenty of good simulation tools, so why reinvent the wheel? However, if you are only using the basic workflow of Yosys, Arachne-pnr, icepack, and iceprog, you could be missing out on some of the most interesting features. Let’s take a deeper look.

Yosys Options

Yosys is software that converts your Verilog into a BLIF file which stands for Berkeley Logic Interchange Format. It has an interactive command line, but most people use it with a command string as part of a script. For example:

yosys -p "synth_ice40 blif demo.blif" demo.v

The synth_ice40 is sort of a script, though, and it does quite a few operations for you. There are other commands you can use, too:

• check – The check command looks for errors in whatever you have loaded so far.
• show – Generates a “schematic” using graphviz (see below).
• write_verilog – You can write out an intermediate Verilog which might be useful to simulate to run down synthesis issues if you have a simulation library for the FPGA primatives.
• write_spice – You can also write out a Spice net list if you prefer.

Note that at the time I’m writing this, there’s a bug in the documentation page where — starting with attrmvcp — the descriptions are one off. That is, the description for chparm is supposed to be the description for check, for example. Perhaps it has been fixed by now. You might also notice a reference to commands to read VHDL automatically through a translator. Don’t get excited, because this has been removed in recent versions since all of the translators have some issues with certain VHDL. Of course, if it works for you, it is possible to do that conversion before calling yosys, if you like. There’s also a plugin for using vhdl2vl if you are brave. Or just stick with Verilog.

An Example

Just to look at a few of these features, here’s a really simple piece of Verilog that won’t win any prizes:

module test(input clk, input reset, input a, input b, input enable, output reg q);
wire q_intermediate;
assign q_intermediate=a^b;

// enable next line to see an error

// always @(posedge clk) q<=1'b1;
always @(posedge clk)
if (reset)
q<=1'b0;
else
if (enable) q<=q_intermediate;

endmodule

This module XORs the a and b inputs and latches the value on q at the rising clock edge if the input enable is high. Simple.

Instead of giving yosys a command line, just run yosys with no options. You’ll get a prompt. If you try entering the check command, you’ll get a message that you need to run …read more

Source:: Hackaday